1. Field of the Invention
This invention relates to a semiconductor storage device which transfers data stored in a memory array to the outside in response to a read command, and particularly relates to a semiconductor storage device having a configuration for prefetching data of a predetermined number of bits to store in a output buffer circuit and transferring the data sequentially from the output buffer circuit to the outside.
2. Related Art
In recent yeas, in order to control systems using semiconductor storage devices such as a DRAM (dynamic random access memories), there is a need for a technology for transferring data to the outside at high speed. For example, a DDR SDRAM (double-data-rate synchronous DRAMs) synchronizes with both rising and falling edges of an external clock to achieve higher-speed data transfer. In general, when data is read from the DRAM, access time from when a read command is issued until read data is output is determined by a predetermined number of cycles of the external clock. The number of cycles of the external clock is preset as CAS (column address strobe) latency, and when the amount of time corresponding to the number of cycles of the CAS latency passes after the read command is received, the read data is transferred to the outside. In recent years, due to rapid advances in speeding up the external clock, there is a tendency that the CAS latency increases.
In general, since speeding up the internal operation of the DRAM is limited, a configuration in which data located at consecutive addresses are read, a predetermined number of bits are prefetched, and the prefetched bits are transferred in parallel to an output buffer circuit and are stored therein is employed in order to adjust the speed of the internal operation and the high speed of transferring data to the outside (e.g., refer to Japanese Unexamined Patent Application Publication No. 2001-243770). For example, control is performed such that prefetched data of a plurality of bits is pre-stored in the output buffer circuit and, when the aforementioned access time arrives, the data is serially transferred in synchronization with the external clock. By this, the external transfer speed can be increased several-fold relative to the internal operation speed.
On the other hand, a burst read operation in which addresses are updated at predetermined intervals and data is continuously read and output in sequence is known as a read operation. When such a burst read operation is performed, at timing when data for which a read command has been previously issued is still stored in the output buffer circuit, data for which a read command is subsequently issued may be further stored therein. Thus, in order to prevent malfunction caused by overwriting of the output buffer circuit, it is necessary to configure the output buffer circuit with multistage FIFO (first in, first-out) buffer and to perform control so that input data is stored during a predetermined time and is sequentially output in accordance with the input sequence.
In general, it is required that access to the DRAM conforms to various operating conditions, including the frequency of the external clock and so on. In this case, the number of stages of the aforementioned FIFO buffer and the value of the CAS latency must be set so as to ensure a proper operation even in the worst operating condition. For example, during the burst read operation, the access time increases as the frequency of the external clock decreases, whereas the timing at which data is transferred to the output buffer circuit comes relatively early. Thus, there is a need to enable the output buffer circuit to reliably store data even in such an operation condition. In contrast, when the frequency of the external clock increases, the timing at which data is transferred to the output buffer circuit is delayed relative to the access time under the same condition. Thus, the amount of data to be stored in the output buffer circuit is essentially small. Accordingly, when configuring the output buffer circuit which conforms the worst operating condition in which the external clock has a wide frequency range, unnecessary circuitry for data storage increases. In this case, particularly when a high-speed external clock is used, the unnecessary circuitry in the output buffer circuit causes problems, such as an increase in the scale of circuitry operating in the output buffer circuit and an increase in the number of control-signal lines. A combination of the factors described above causes a problem in that, particularly, current consumed during high-speed access to the DRAM increases.